1. OBJECTIVE Design Tar stay put/ accusative/calculation 1. To design a lap which pass on have the following criteria: a. stripped chip area b. stripped transistor count c. nominal power dissipation d. Minimum propagation hamper (maximum speed possible) 2. To vex the hand-analyze of the chosen lap architecture to get maximum performance 3. To prepare the stimulant test vectors and the expected results 4. To produce the testing methodology 5. To set up the travel is functional and meet every design spec 6. To extract the simulation results. 7. To analyze the differences among the results for hand-analysis, schematic delight and layout 2. sketch FUNCTIONAL EXPLANATION The project performed by this team go forth be the 4 bit parallel jet viper. The head start tincture in creating this is to focus in invention a 1 bit common viper first. Given down the stairs is a configuration of a 1 bit adder. The first stage of the adder is a XNOR logic gate that has an output potential of VDD VTN where A and B are both VDD inputs. A broad voltage sail XOR gate signal is generated using an inverter. This XOR gate and Cin input signals depart cooperate to generate Cout and SUM outputs with a maximum of iodin VT loss.

Figure 1: 1-bit adder CMOS circuit This one bit adder after being intentional in mentor artistic creation allow for be confined into a simple emblem below. This figure will be repeated four times. The Cout will be carried in front until the 4th adder. The symbol is shown be low. Figure 2: !-bit adder symbol Figur! e 2: 1-bit adder CMOS symbol The fn-out are detached from the fan-in using buffer circuits at the inputs and the outputs. They will also dish out to smoothen the output voltages and reduce the propagation delay of the boilersuit adder. 3. DESIGN METHODOLOGY AND FLOW Specification / Definition formal Entry Simulation Pass? stimulus Stimulus Layout DRC/LVS epenthetic Extraction Post-layout Simulation Tape-out Input Stimulus Pass? No No Yes Yes...If you want to get a full essay, gear up it on our website:
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